Timing-Driven Placement using Design Hierarchy Guided Constraint Generation

Design hierarchy plays an important role in timing-driven placement for large circuits. In this paper, we present a new methodology for delay budgeting based timing-driven placement. A novel slack assignment approach is described as well as its application on delay budgeting with design hierarchy information. The proposed timing-driven placement flow is evaluated using an industrial place and route flow. All results are reported after detailed routing and timing analysis. Compared to Cadence QPlace, the proposed placement flow generates placements with shorter clock cycle and better routability. Our preliminary experimental results show that considering design hierarchy is a promising way to handle timing optimization problem.